A static random access memory (hereinafter, referred to as SRAM) is known as a type of static semiconductor storage devices.
In SRAMs, memory cells having, for example, six transistors, are arrayed in rows and columns. These memory cells are connected to a plurality of word lines extended in a row direction and to a plurality of pairs of bit lines extended in a column direction. The transistors paired to constitute each memory cell are cross connected and connected to the bit lines. In addition, nodes of these transistors are connected to a pair of switching transistors, which are connected to the word line.
When a large number of memory cells are connected to a pair of bit lines in the column direction, the bit lines are loaded with capacitance. Accordingly, a sense amplifier amplifies very small amplitude of an output signal from the selected pair of bit lines, in order to read out data stored in the selected memory cell.
The sense amplifier is required to have a sufficiently low input offset, in order to sense the very small amplitude for high-speed readout operation. In order to achieve this, an area of the sense amplifier must be enlarged.
However, an influence of the dispersion of characteristics of each element becomes more serious as the devices are miniaturized. As a result, it is gradually becoming difficult to produce a sense amplifier with a sufficiently small input offset.
Thus, instead of sensing the very small amplitude, it is considered to reduce the number of the memory cells connected to each pair of bit lines in the column direction, to lighten the capacitive load of the bit lines. For this purpose, the bit lines are divided in the column direction to read out data from each divided pair of the bit lines.
In an SRAM of single-end sensing type, each memory cell is connected to a pair of local bit lines. Furthermore, the pair of local bit lines is connected to a pair of global bit lines through switching transistors. One of the pair of local bit lines is connected to a sense amplifier to be used for single-end sensing.
For example, the sense amplifier to be used for the single-end sensing includes an inverter circuit connected to the local bit lines, and an n-channel transistor having a gate connected to the inverter circuit. Such an SRAM is referred to as single-end sensing type.
The switching transistors of the memory cell are conductive by be setting the word lines to level 1 to read out data. Accordingly, the memory cell is electrically coupled with the pair of local bit lines. In an SRAM of the single-end sensing type, capacitance of each pair of local bit lines is sufficiently low. Therefore, data stored in the memory cell can be outputted by increasing the electric potential of one of the pair of local bit lines in full range from earthed potential (0V) to power supply potential (VDD).
Accordingly, when reading out data stored in the memory cell, the signal from the memory cell can be sufficiently amplified by a logic gate such as an inverter circuit to sense the data.
In the case where the output of one of the selected pair of local bit lines is level 0, the n-channel transistors of the sense amplifier are conductive, and global bit lines are forced to be level 0 when reading out the data from the memory cell.
On the contrary, when the output of one of the selected pair of local bit lines is level 1, the n-channel transistors of the sense amplifier are nonconductive. Since the initial settings of the global bit lines are pulled up, level 1 is outputted from the global bit lines.
As described above, it is unnecessary to provide a sense amplifier with an input offset reduced by enlarging its area in the SRAM of the single-end sensing type, unlike normal SRAMs. Thus, it is possible to substitute a logic gate such as an NAND circuit or an inverter circuit with a small area for a sense amplifier as described in Kevin Zhang, Ken Hose, Vivek De, and Borys Senyk et al, “The Scaling of Data Sensing Schemes for High Speed Cache Design in Sub-0.18 μm Technologies,” 2000 symposium on VLSI Circuits Digest of Technical Papers, P.226-227.
To write data into the SRAM of the single-end sensing type, one of the pulled-up pair of local bit lines connected to the memory cell becomes level 0. As a result, each pair of the global bit lines is required to exist for each pair of the local bit lines.
A plurality of these pairs of global bit lines are usually wired by use of upper layer metal. When a large number of the global bit lines are wired, pitches are reduced between the lines. Accordingly, capacitance is increased between the lines. Furthermore, to prevent the pitches between the lines from reducing, widths between the lines may be narrowed. However, resistance of the lines themselves increases.
These factors incur increase in wiring delay in the global bits lines and reduce the operation speed.